1. Field of the Invention
This invention relates generally to semiconductor memory devices and more particularly to a semiconductor memory device capable of recovering or “rescuing” data defects occurring due to the quest for lower electrical power consumption.
2. Description of the Related Art
As semiconductor memory devices decrease in size and power dissipation while increasing in storage capacity, it is becoming more difficult for memory cells of such semiconductor memories, in particular those having ultrafine or “micro” structures, to attain high reliability in view of fabrication process technologies and also transistor characteristics. Semiconductor memories include static random access memory (SRAM) chips with an array of memory cells, each of which is formed of a plurality of transistors—in traditional SRAM cells of the full complementary metal oxide semiconductor (CMOS) type, six separate transistors are used on a per-cell basis. Due to the use of multiple transistors per cell, SRAMS suffer from difficulties in achievement of small size and large storage capacity. In contrast thereto, dynamic random access memory (DRAM) chips are such that a memory cell consists essentially of a single transistor and one capacitor, which enables DRAMs to be better suited for achievement of small sizes and large storage capacities.
In light of these characteristics of SRAMs and DRAMs, in small size portable or handheld electronic equipment such as for example mobile wireless telephone handsets, personal digital assistants (PDAs), note pads, palm-top personal computers (PCs) or the like, it has been considered to achieve smaller size (higher density) by replacing part of prior known memory systems using SRAMs with a new type of memory chips using DRAM-based cells with SRAM interface architectures, also known as Pseudo SRAMs or “PSRAMs.” Generally, DRAMs are designed to perform multiplex row and column addresses; on the contrary, SRAMs perform no such address multiplexing. Accordingly, direct use of SRAM interface would result in PSRAMs being used with the lack of any address multiplexing. In addition, DRAMs call for execution of data refresh operations; thus, it becomes necessary for PSRAMs also to contain internal automatic refresh circuitry as built therein.
It is apparent from the foregoing discussion that the use of PSRAMs enables achievement of smaller system sizes and thus larger storage capacities (higher integration densities), although this approach accompanies a penalty that PSRAMs become greater in data retain currents than SRAMs due to employment of DRAM-based cell designs. Unfortunately, in cases where an attempt is made to achieve further reduced power consumption, the resultant memory cells decrease in data retaining characteristics. The degradation of data storing performance causes a problem as to unwanted generation of defective data even when PSRAMs are designed to come with on-chip automatic refresh circuitry.
The data storability degradation due to employment of advanced power save technologies is not a problem unique to PSRAMs per se. It can cause problems in standard DRAMs and also in electrically erasable and programmable read-only memory (EEPROM) chips.